The structure is very similar to that of a vertically diffused MOSFET featuring a double diffusion of a p-type region and an n-type region. An inversion layer can be formed under the gate by applying the correct voltage to the gate contact as with a MOSFET. The main difference is the use of a p+ substrate layer for the drain. The effect is to change this into a bipolar device as this p-type region injects holes into the n-type drift region.
The on/off state of the device is controlled, as in a MOSFET, by the gate voltage VG. If the voltage applied to the gate contact, with respect to the emitter, is less than the threshold voltage Vth then no MOSFET inversion layer is created and the device is turned off. When this is the case, any applied forward voltage will fall across the reversed biased junction J2. The only current to flow will be a small leakage current.
The forward breakdown voltage is therefore determined by the breakdown voltage of this junction. This is an important factor, particularly for power devices where large voltages and currents are being dealt with. The breakdown voltage of the one-sided junction is dependent on the doping of the lower-doped side of the junction, i.e. the n- side. This is because the lower doping results in a wider depletion region and thus a lower maximum electric field in the depletion region. It is for this reason that the n- drift region is doped much lighter than the p-type body region. The device that is being modelled is designed to have a breakdown voltage of 600V.
The n+ buffer layer is often present to prevent the depletion region of junction J2 from extending right to the p bipolar collector. The inclusion of this layer however drastically reduces the reverse blocking capability of the device as this is dependent on the breakdown voltage of junction J3, which is reverse biased under reverse voltage conditions. The benefit of this buffer layer is that it allows the thickness of the drift region to be reduced, thus reducing on-state losses.
The turning on of the device is achieved by increasing the gate voltage VG so that it is greater than the threshold voltage Vth. This results in an inversion layer forming under the gate which provides a channel linking the source to the drift region of the device. Electrons are then injected from the source into the drift region while at the same time junction J3, which is forward biased, injects holes into the n- doped drift region (Fig.2).
Fig.3(b) shows a more complete equivalent circuit which includes the parasitic npn transistor formed by the n+-type MOSFET source, the p-type body region and the n--type drift region. Also shown is the lateral resistance of the p-type region. If the current flowing through this resistance is high enough it will produce a voltage drop that will forward bias the junction with the n+ region turning on the parasitic transistor which forms part of a parasitic thyristor. Once this happens there is a high injection of electrons from the n+ region into the p region and all gate control is lost. This is known as latch up and usually leads to device destruction.
Nombre: Lenny Ramirez
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