lunes, 28 de junio de 2010

Modeling of Integrated Circuit Defect Sensitivities

Pinhole defects

One class of defects, known as pinholes, occurs in dielectric insulators such as thin and thick silicon oxides, oxidized poly silicon, chemical vapor deposited insulators, quartz, etc.
These defects are usually much smaller than a micrometer.
Their occurrence can result in a short circuit between conductors produced at different photolithographic levels.
The area in which such defects cause failures is the overlap region between two conductors that cross each other, as shown in Fig. 1. Defects that fall outside these overlap areas cannot cause short circuits. We call the overlap where failures do occur the "critical area." The words "defect sensitive area" and "susceptible area" have also been used in the same context.
Critical areas of pinholes in most designs can be determined readily as the total overlap area between patterns at different photolithographic levels. When the integrated circuit masks are generated with a computer, algorithms are often available to determine this area fo r an entire chip. The result must be less than the total chip area. Let 0 be the fraction of chip area A that is sensitive to pinholes. The critical area Ac can then be expressed as
Ac = 0A.
The average number of failures or faults caused by the defects can now be calculated by
X = AcD
= θADc
Where D is the density of defects per unit area. This is the direct relationship between defect densities and the average number of faults that also was discussed in previous papers
Some investigations into the defect densities of dielectric pinholes have shown that the average numbeorf failures per monitor can be proportional to the monitor length [4]. A typical structure where this can occur is shown in the cross section of a charge-coupled device in Fig. 2. Stress effects between the two polysilicon patterns create defects a long the edges of the overlap area.
To model these effects one has to count the number of faults that occur along an overlap section of length L. It is then possible to define
X = LD,
Where DL is the density in defects per unit length. This is a model that differs significantly from the area model, since the defect densities are in different units. Yet, if both the area and the length pinhole effects take place in the same chip, their combined number of faults is given by
550 X = AcD + LD,
This result demonstrates an important principle in yield modeling: Faults caused by different failure mechanisms can be added, but defect densities for different failure mechanisms cannot be added. In this example the defect densities have to be modified by both the critical area and the critical length to become faults.
It is possible at this point to expose a myth that seems to recur constantly in yield models used by the semiconductor industry. This myth assumes that the yield can be modeled with only one critical area and one defect density, regardless of the process complexity. Even though thus far we have discussed only one defect type, namely, pinholes, we already see that such an averaging process is impossible. It should be clear that the introduction of other defect types should make this simplification even less likely. The only simplification possible is the use of the cumulative average number of faults X to which all these defects contribute.

Pinhole defect monitors

The relationship between the average number of faults for area pinholes and the defect density D is a simple proportionality.
This simplicity has a useful application. If we have a process without a linear pinhole problem, we can make defect monitors that consist only of a large overlap area between two conductors. By measuring the resistance between the conductors, we can determine when the monitors are short circuited and fail due to pinholes.
Let us assume that we have made N of these monitors and we find that U of these are short-circuited. The monitor yield Y, is then given by
Ym= (N-U)/N
We now want to estimate the average number of faults that cause these failures. Unfortunately, we have no way of knowing how many faults cause a monitor to fail. In most cases it is only one fault, but there canb e instances in which two or more defects cause two or more faults. If the defect density is constant in the sample and the defects occur at random, then the distribution of the number of faults per monitor is given by a Poisson distribution

Photolithographic defects
Patterns of polysilicon, metal, dielectric insulators, and diffusions in silicon wafer surfaces are used to make and interconnect the transistors, diodes, resistors, and capacitors in integrated circuit chips. Minimum pattern dimensions of a few micrometers are typical for the integrated circuits manufactured today. Dust and dirt particles with similar dimensions, or larger, are the major cause of defects in integrated circuit production. Such particles interfere with the photolithographic processes used to define the patterns. Whether a particle causes a failure depends on its location on a chip or on the photographic misused in the process. The size of the resulting defect also determines whether the chip will fail. In many cases small defects don ot cause chip failures a t all.
A theory for mathematically modeling the size dependency of defects was originally developed by R. H. Dennard and P.C o ok at the IBM ThomaJs. Watson Research Center, Yorktown Heights, New York, in the late 1960s. This theory has subsequently been adapted by Madder et al. in a yield model used for manufacturing control. Other yield models that make use of this approach have since been applied for yield projection and line control at a number of IBM manufacturing locations. However, until now only a cursory description of the defect size model has been given in the literature. It is the purpose of the next sections to describe them odel and derive it from fundamental principles.
Critical areas of very long conductors
The effect of defect size on integrated circuit patterns is best approached by first considering a very long straight conductive line. We assume that this conductor is deposited on an insulator and has a length L which is much greater than its width w. This conductive line has to allow an electric current to flow from one end to the other. The failures this case is open circuits caused by holes in the conductive material.
These holes are referred to as missing photolithographic patterns.
It must be pointed out here that there is a class of open circuits that is caused by minute cracks in the conductive material. This usually occurs where the conductor passes over steps from the edges of the patterns underneath. Such defects can be modeled by counting the number of critical steps in a design. This propensity of steps to cause discontinuities can be measured with defect monitors. These defects are not included in the analysis which follows.
When photolithographic defects are very small, there can be enough conductive material left to allow the line to conduct currents without failure. Such a condition is depicted in Fig. 3. We define the defect size as a maximum defect dimension perpendicular to the line edges.

The width of the defect in the longitudinal or horizontal dimension does not matter. In actual cases it is usually of the same magnitude as the universe dimension. It has therefore proven convenient to model the defects as circles, as is done in the rest of this paper. The diameter of each circular defect is designated with the Greek letterx.
The object of our model is to find the mathematical relationship between the critical area and the desfeizcet. We have already seen that for small enough defects the conductor will not fail. We now must consider the maximum amount of conductive material that can be left by a defect and have it still cause a failure. If more than this amount is left, the line will not fail. When less than this amount remains, the line will always fail.
The amount to f the conductor that has left by a defect in order not to cause a failure during final test depends on the electrical current that flows through the line when it is tested.
In this paper we focus attention on models for final test or functional yield of chips. Reliability failures caused by the phenomenon of aluminum migration can be modeled with a similar model but are not treated in this paper. We assume that, during normal operation and final test, the conductor carries enough current to make it "blow" when only a width d of material is left. If the width is greater than d, we assume that the line is not affected, while any amount of material of width d or less always causes a failure.
Thus defects of size x < (w - d) leave enough conductive material to keep the conductor operational, and defects of size x 2 (w - d) cause the line to fail if they occur in the right location. These conditions are known as the failure criteria. The locus of the center of defects that lead to failure is known as the critical area. The critical area is therefore defined as the area in which the center of a defect must fall to cause a failure or a fault.
Let us first determine the critical area for a defect of size
x = (w - d). This area is indicated by the dashed lines in Fig. 4. If the center of the defect falls above the upper dashed line, no failure will occur. Similarly, if the defect is centered below the lower dashed line, there will be no fault. In both these cases more than a width d of conductive material is left.
With the drawing in Fig. 4 we can determine the distance between either edge of the conductor and it's nearest dashed line. This distance is equal to the radius of the defect, which is (w - d) / 2. The space between the two dashed lines of Fig.4 is therefore equal to d, the same distance afso r the failure criteria. We obtain the critical area by multiplying the line length by the distance to get and area LD. This is an interesting result. For defects smaller than size (w - d) the critical area was zero. Then all of a sudden at defect size (w - d) we find a critical area equal to Ld. The critical area is therefore discontinuous. This is a direct consequence of the minimum allowable line width assumption used in the derivation of this critical area.
Next we must determine the critical areas for defects that are larger than (w ~ d). This critical area depends on the defect size. The diagram in Fig. 5 should be helpful in the analysis of this dependency. A defect shown in this diagram is positioned in the uppermost location where it will cause a fault during test. If it were located just a little higher, it would leave a strip of material that is wider than distance d. In that case no failure would occur during testing.


In integrated circuit manufacturing large numbers of different defects cause yield losses. Each defect type has its own mechanism to cause a chip faille. In this paper defects have been categorized into two classes. Defects for which the defect size is not important are the easiest to model and are considered in the first class, e.g., defects that cause dielectric pinholes and junction leakage. The second class pertains to defects that are comparable in size to the photolithographic patterns. In this case the defect sensitivity depends on the defect size. We have shown a simple example of how this can be handled. All photolithographic defects fall into this category.
Defect monitors tie in very well with defect sensitivity models. Monitor data are used to measure the average number of failures and determine defect densities. For photolithographic defects the monitors have been used to find the defect size distribution and establish the capabilities and limits of photolithographic technologies.

Lenny Z Perez M

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